SoC/ASIC Design Verification Engineer
Company: zeroRISC
Location: Boston
Posted on: February 15, 2026
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Job Description:
Job Description Job Description zeroRISC zeroRISC is redefining
chip security and supply chain integrity by empowering device
owners and operators in crucial sectors like silicon production,
IoT, and critical infrastructure with full device ownership,
control, and visibility. Led by the founders of the OpenTitan
secure silicon project, zeroRISC is driving commercial adoption of
high assurance software and services rooted in open silicon. Our
products forge an immutable connection between hardware and
software, enabling users to trust their devices no matter where
they’re built or where they’re deployed. Role Overview As a
zeroRISC SoC/ASIC Design Verification Engineer, you will develop,
verify, and maintain silicon in security-sensitive settings,
including root-of-trust technology. You will elevate and solidify
zeroRISC's status as the leading provider of secure silicon IP by
developing essential verification collateral. You will interact
directly with zeroRISC customers to understand their requirements
and deliver solutions benefitting both customer and zeroRISC alike.
You will participate in the whole chip design process from
architecture to tapeout and silicon validation. By engaging with
the world's premier open-source silicon community, you will support
our mission of open secure silicon everywhere. We're looking for
engineers with strong design verification skills (and a long view
of secure system architecture) who are also fast, flexible learners
and enthusiastic about open source. Key Responsibilities: Verify
ASIC/SoC functionality, performance, security, and power throughout
the full chip design life cycle, from test plan definition to
sign-off Build high quality verification environments at the
chip/top and block levels following engineering best practices
Write thorough verification documentation including test plans
Diagnose, debug, and resolve regression failures and other errors
Achieve coverage closure Ensure design functionality while
upholding stringent timelines in collaboration with architecture,
design, software, system, and silicon validation teams as well as
engineering program managers What We’re Looking For: Bachelor’s
degree in Electrical Engineering or Computer Science, or a related
technical field or equivalent experience 4 years of experience with
simulation-based verification methodologies and languages such as
UVM and SystemVerilog or formal verification-based techniques
including industry standard tools Experience developing and
maintaining testbenches, test cases, and verification environments
for simulation-based verification or formal verification
environments Preferred Qualifications (not required): Master’s or
PhD in Electrical Engineering or Computer Science, or a related
technical field or equivalent experience Knowledge of security
ASICs or accelerators (e.g. cryptography accelerators or GPUs)
Knowledge of computer architecture and memory subsystem
architectures Experience verifying low power designs Experience
with scripting languages such as Python Why Join Us? Your work will
directly contribute to the development of cutting-edge security
solutions, protecting critical systems in industrial and IoT
environments As a seed-stage startup, this role offers significant
opportunities for learning and career growth Join a close-knit,
innovative team where you can learn, grow, and contribute to
building something meaningful in the security space We may use
artificial intelligence (AI) tools to support parts of the hiring
process, such as reviewing applications, analyzing resumes, or
assessing responses. These tools assist our recruitment team but do
not replace human judgment. Final hiring decisions are ultimately
made by humans. If you would like more information about how your
data is processed, please contact us.
Keywords: zeroRISC, Salem , SoC/ASIC Design Verification Engineer, Engineering , Boston, Massachusetts
